Date and time
Thursday 2 October 2008, 9:00 - 17:00
Description
Recognising that we are on the verge of exciting new accelerated computer hardware technologies that enable significant computational capacity and exceptional performance, is a cornerstone of this workshop. Graphics processing unit (GPUs) are a powerful and cost-effective platform for high performance parallel computing; particularity for computational intensive data parallel applications. The current generation of GPUs have capabilities in TFLOP range, and have 32.768M parallel thread capacity. Such an increase in computational power opens opportunities to explore previously inaccessible problems in many scientific domains. However, it also brings the challenges of adapting existing algorithms and codes (and devising new ones) to run efficiently on GPU architectures.
This workshop will cover recent advances in programmable graphics processors and the functionality into general purpose computing. This workshop will bring together experts from the two leading GPU developers: NVIDIA (Mark Harris) and AMD (Justin). Both will provide insights into GPU and Stream computing practices and experiences. Karen Haines from the WASP@UWA, will also present insights into the challenges of developing coursework suitable to training the next generation of software developers. These perspectives on developing and adapting software to exploit the GPU’s capabilities are crucial to understanding the challenges of the massively threaded processors.
Provisional outline
Session I: NVIDA/CUDA Programming (Mark Harris)
- Introduction/Overview
- GPU Architecture & Applications
- Parallel Computing in CUDA
- CUDA Libraries
- Optimizing CUDA
- Wrap - up (including NVIDIA Collaboration Opportunities)
Session II: AMD Stream Computing (Justin Hensley)
- Introduction and data-parallel programming (GPU-style)
- Overview of AMD GPU architecture
- AMD's GPU accelerated libraries
- Overview of AMD's FireStream SDK
- Performance tuning
- Conclusion and discussion
Session III: Educating Next Generation Software Developers (Karen Haines)
- Approaches that will last through the fast changing hardware developments
- Planning for the next-generation mindset
About the presenters
Mark Harris, NVIDIA Research
Mark Harris is a member of the Developer Technology team at NVIDIA, where he works with developers around the world on software for computer graphics and high-performance computing. His research interests include parallel computing, general-purpose computation on GPUs, physically based simulation, real-time rendering, and gastronomy. Mark earned his Ph.D. in computer science from the University of North Carolina at Chapel Hill in 2003 and his B.S. from the University of Notre Dame in 1998. Mark founded and maintains GPGPU.org, a web site dedicated to general-purpose computation on GPUs. Mark has recently moved to Australia after living in the United Kingdom for five years.
Justin Hensley, Advanced Micro Devices Inc.
Justin Hensley is an architect in AMD’s Graphics Product Group Office of the CTO focusing on parallel programming using graphics processors. Since joining AMD, Justin has been involved with several projects including face recognition, depth extraction, game physics. Recently, he has been involved with driving the compute requirements, and the associated software stacks, of next generation graphics processors. Justin received his Ph.D. in Computer Science from the University of North Carolina at Chapel Hill in 2007. He also holds an M.S. Electrical Engineering and a B.S. with a double major in Electrical Engineering and Computer Science Engineering from the University of California at Davis.
Karen Haines, The University of Western Australia
A/Prof Karen Haines is the Director of the WASP. She came to UWA in 2002 from the Albuquerque High Performance Computing Centre at the University of New Mexico, where she was responsible for providing workshops and guidance in the areas of parallel programming and scientific visualization. A/Prof Haines was instrumental in instituting the WASP. In addition to directing the WASP, she is responsible for providing workshops and guidance in the areas of distributed parallel programming, and GPU Programming. A/Prof Haines completed her PhD in Electrical Engineering at the University of New Mexico. She received her Masters in Engineering at Carnegie Mellon University and her Bachelor of Arts in Mathematics at the University of California, San Diego.